Lateral bipolar transistors, normally PNP transistors, formed in integrated circuits have a variety of applications. Their method of fabrication depends on the voltages to which they will be subjected to in use and there are characteristically different processes for the three voltage ranges (1 ) less than 5 volts, (2) between 5 and 12 to 14 volts and (3) between 14 and 25 volts. One of the critical parameters is that of width of isolation between active regions to prevent electrical breakdown between active regions in the condition of maximum operating voltage. In particular, for case (2) where the lateral transistor is designed as a power transistor to operate with voltages up to 12 or 14 volts, it is important to minimize dimensions of the transistor in order to reduce parasitic resistances, while maintaining adequate spacing between active regions to ensure that breakdown does not occur on maximum operating voltage.
In the prior art, such lateral pnp transistors are formed in large numbers on a common substrate together with vertical npn transistors. In the prior art, a p-type substrate has an n-type epitaxial layer formed thereon. Above this a silicon oxide layer is formed and then subsequently a silicon nitride layer which is employed to form a master mask. The master mask defines the isolation and base regions of the vertical npn transistors, and a further oversize isolation mask is employed to cover the base region while the isolation regions are formed by boron diffusion. The isolation mask is then removed to permit doping of an npn base region. Emitter and collector regions are formed and processed using extra masks, with consequent alignment problems.
A problem in the past has been that because of alignment tolerances in the process arising from the various processing masks superimposed on the substrate, it has been necessary to make the dimensions of the transistor relatively large in order to accommodate these tolerances. This has the disadvantage of extra size and consequent increased parasitic resistances.
U.S. Pat. No. 4,837,176 discloses the formation of a lateral transistor using a master mask. However the patent is concerned with planarisation of polysilicon layers and is not concerned with the present problems.